The present invention relates to very high speed analog-to-digital (A/D) converters and, in particular, to an A/D converter having an auto-zeroed latching comparator.
High speed A/D converters commonly use an architecture known as a flash architecture. The simplest type of N-bit flash A/D converter requires 2.sup.N comparators. These comparators are usually of a sampling type, in which a voltage comparison is made between the comparator's differential inputs upon the transition of a clock input. Good linearity performance of the A/D converter requires that the input offset voltage of each sampling comparator be minimized.
A typical method of nulling the input offset voltage involves measuring and storing the offset voltage on a sampling capacitor, followed by inserting the capacitor in series with the signal path. This method requires specialized circuitry and a certain sequence of operations such that the measured voltage exactly cancels the offset voltage of the comparator. A difficulty with this method is that the sampling capacitor results in a higher comparator input capacitance due to parasitic coupling of the sampling capacitor to the integrated circuit substrate on which the comparator is fabricated. Also, the sampling capacitor and the specialized track/hold and offset cancellation circuitry consume a relatively large area on the integrated circuit.